Halo implant methods have been used to improve a short channel effect (SCE) in planar field effect transistors (“FETs”). Typically, an angled halo ion implantation with dopants of opposite polarity from that of the source and drain regions is used to increase the substrate doping adjacent to the source and drain regions of an FET in a way that effectively reduces the extent of the source and drain at the edges and/or under the sidewall spacers but at some depth below the semiconductor substrate surface.
Compared to the most advanced planar FET devices, a fin-shaped field effect transistor (“FinFET”) provides lower power due to the fully depleted (lightly doped) thin body of the fin and the resulting reduced or reverse SCE with improved drain-induced barrier lowering (DIBL). A FinFET generally has a lightly doped channel and less random dopant fluctuation (RDF) than a planar FET.
Low power is increasingly important as device size decreases, particularly for radio frequency (RF) analog circuit design and system-on-chip (SoC) applications, because most RF/analog transistors tend to operate in the saturation region for a higher transconductance. However, as yet, FinFETs for analog applications have not been fully optimized for low power operation.
Auth et al. (“A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” IEEE Symposium on VSLI Technology, 131-32, 2012, incorporated herein by reference) disclose performance parameters for Intel's tri-gate transistor technology now in volume production. Neither these FinFETs nor others in development take advantage of halo or super-halo implants to improve performance. Super-halo methods have so far been used only in planar FETs, as discussed, for example, in Liu et al. (“Fluorine-assisted super-halo for sub-50 nm transistor,” IEEE Electron Device Letters, 24 (3), 180-82, 2003 incorporated herein by reference).